This invention relates to the field of semiconductor technology and, more particularly, to the field of shallow trench isolation.
As the dimensions and feature sizes of semiconductor devices become increasingly smaller, the electrical isolation of individual devices on a chip becomes progressively more challenging. Each device on an integrated circuit chip must be electrically isolated from neighboring devices in order to enable the independent operation of the device and to prevent short-circuiting.
One of the most widely used techniques for the isolation of semiconductor devices is known as shallow trench isolation (STI). The typical steps involved in the fabrication of an STI structure in a semiconductor substrate are illustrated in FIGS. 1-4. The semiconductor substrate 2 shown in FIG. 1 is made by forming a pad (or buffer) oxide layer 4 over a silicon layer 6. A nitride layer 8 is then deposited over the pad oxide layer 4. A photoresist layer 10 is then deposited over nitride layer 8 and patterned using photolithography to create a soft mask opening 12. The nitride layer 8 and oxide layer 4 are successively etched through soft mask opening 12 to create an opening 14, as shown in FIG. 2. Silicon layer 6 is then etched through opening 14 to form a shallow trench 16. In general, etching of the nitride layer 8, pad oxide layer 4, and silicon layer 6 is desirably achieved by anisotropic etching, such that the sidewalls of the trench formed are vertical. Photoresist 10 is removed and trench 16 is filled with a dielectric material 17 (e.g., an oxide) to provide the structure shown in FIG. 3. Chemical mechanical polishing (CMP) of this structure and removal of nitride layer 8 and pad oxide layer 4 completes the process, and provides the shallow trench isolation structure 18 shown in FIG. 4.
While STI technology has proven to be a highly effective isolation technique—one that avoids the undesirable Bird's Beak formation encountered in other isolation methodologies, such as localized oxidation of silicon (LOCOS)—the performance characteristics of devices created by STI etching can be adversely affected by the presence of sharp bottom corners 20 and sharp top corners 22 on the trench 16. Sharp bottom corners 20 may result in high stress, which leads to lattice defects in the single-crystal silicon substrate during liner oxidation, and during the subsequent filling of the trench with dielectric material. Sharp top corners 22 may result in junction leakage currents, lowered threshold voltages, and unwanted increases in sub-threshold currents when the field effect transistors (FETs) are activated. In view of these pitfalls, it is generally desirable in STI etching to form trenches having rounded top and bottom corners.
Furthermore, in order to produce semiconductor devices having high quality performance characteristics, it is desirable to reduce the number of defects formed in the silicon trench. Defects may be introduced into the semiconductor structure during deposition of the individual layers. In addition, defects may be introduced as a result of the phenomenon known as micromasking. Briefly stated, micromasking structures (also known as “cone-shaped defects” and “spikes”) are generally caused by residual polymeric material produced from the etching chemistries used to etch nitride layer 8 and pad oxide layer 4. In order to achieve the corner rounding described above, it is common to employ a polymerizing chemistry to etch the oxide layer. Polymeric material is deposited on the sidewalls, which will then block the eventual silicon etch in such a way so as to cause rounding of the corners of the trench. However, residual polymeric material 21 also accumulates along the interface between adjacent layers, such as between nitride layer 8 and pad oxide layer 4, and blocks the subsequent etching of silicon layer 6 in such a way as to create cone or spike defects 19 in the silicon trench 16, as shown in FIG. 5. The defect 19 represented with a broken line in FIG. 5 can extend the entire distance from trench bottom 38 to polymeric material 21, or any fraction of this distance.
The present invention is directed to providing shallow trench isolation structures having desirable structural profiles (e.g., substantially vertical sidewalls with rounded top and bottom corners), and very low levels of cone-shaped defects.